This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was
JK Flip-Flop Explained | Race Around Condition in JK Flip-Flop | JK Flip- Flop Truth Table, Excitation table and Timing Diagram - ALL ABOUT ELECTRONICS
sec 10 06 to 07 Master--Slave and Edge-Triggered J-K Flip-Flop - YouTube
Solved The following waveform specifies the inputs of a | Chegg.com
JK Flip-flop: Positive Edge Triggered and Negative Edge-Triggered Flip-Flop
The JK Flip-Flop (Quickstart Tutorial)
digital logic - Edge triggering seems to me leaving every circuit in an inconsistent state? - Electrical Engineering Stack Exchange
JK Flip Flop and the Master-Slave JK Flip Flop Tutorial
SOLVED: For a negative edge-triggered J-K flip-flop with inputs as shown in Figure 7, determine the Q output relative to the clock. Assume that Q starts LOW. K For the positive edge-triggered
positive-edge-triggered - Wiktionary, the free dictionary
The JK Flip-Flop
Flip-Flops and Latches - Northwestern Mechatronics Wiki
SOLVED: Consider one positive-edge-triggered JK flip-flop with output Qp and one negative-edge-triggered JK flip-flop with output QN. Assume the Clock, J, and K inputs shown below are applied to the two flip-flops.
Solved 1. Consider the negative edge triggered JK flip-flop | Chegg.com
Solved] Two edge-triggered J-K flip-flops are shown in Figure 7-77. If the... | Course Hero
Edge-Triggered J-K Flip-Flop
Digital Logic Design Engineering Electronics Engineering
Solved For a negative-edge-triggered J-K flip-flop with | Chegg.com
JK Flip-flop: Positive Edge Triggered and Negative Edge-Triggered Flip-Flop